I. Field
The present disclosure relates generally to electronics, and more specifically to a memory device.
II. Background
Memory devices are commonly used in many electronics devices such as computers, wireless communication devices, personal digital assistants (PDAs), etc. A memory device typically includes many rows and columns of memory cells. Each memory cell can store a data value, which is typically either binary ‘0’ or ‘1’. To read a given memory cell in a given row and a given column, a word line for the row is activated, and the memory cell either charges or discharges a bit line for the column depending on the data value stored in the memory cell. A sense amplifier then detects the voltage on the bit line and provides a logic value based on the detected voltage. To write to a given memory cell in a given row and a given column, the word line for the row is activated. A data input driver then drives the bit line for the column either low or high depending on a data value to be written to the memory cell. The data value currently stored in the memory cell is overwritten by the value on the bit line.
For a read operation, the sense amplifier should be turned on as early as possible and for a minimum amount of time in order to achieve high operating speed and low power consumption. The sense amplifier may be activated after the bit line has been sufficiently charged or discharged, so that the data value stored in the memory cell can be reliably detected. This charge/discharge time is dependent on characteristics of transistors in the memory cells and parasitic effects, both of which may vary widely due to variations in integrated circuit (IC) process, power supply voltage, and temperature. For a write operation, the data input driver should be turned on for as long as needed to write a data value into the memory cell. The amount of time needed to write to the memory cell is dependent on the transistor characteristics and parasitic effects.
Process variations are typically more severe as IC fabrication technology improves and transistor size shrinks. The amount of time to allocate for a read operation may be selected based on the worst-case process variations in order to ensure that a bit line is sufficiently charged or discharged prior to sensing. The amount of time to allocate for a write operation may also be selected based on the worst-case process variations in order to ensure that a memory cell is properly written with an input data value. However, designing for the worst-case process variations may result in slower operating speed and/or higher power consumption.
There is therefore a need in the art for a memory device that can efficiently account for process, voltage, and temperature (PVT) variations.